The present invention relates to a semiconductor memory device having a defect relieving system which is applied to, e.g., a dynamic random access memory (to be referred to as a DRAM hereinafter), in particular, in which a data line is replaced depending on an input address.
A large-capacity semiconductor memory device has redundant memory cells and employs a relieving method for replacing a defective memory cell with a redundant memory cell. When such a defective memory cell is relieved, a yield of semiconductor memory devices can be improved.
The total capacity of a semiconductor memory device is a product of a row address R, a column address C, and a data line width (the number of bits) W. In recent years, since a large bus width is strongly demanded, the data line width W increases, and the row address R or the column address C tends to relatively decrease. For example, in case of 64-Mbit DRAM, R=4K, C=1K, and W=16 are conventionally satisfied. However, a DRAM merged to a logic circuit applied to a system-on chip which recently appears satisfies R=4K, C=64, and W=256.
In a conventional DRAM, word lines are replaced with each other depending on a row address, or bit lines are replaced with each other depending on a column address to relief a defective memory cell. However, in this method, when the address width of rows or columns is small, a high relieving rate cannot be obtained without preparing a relatively large number of redundant memory cells.
In a semiconductor memory device having a large data line width, it is known that a high relieving rate can be obtained in a method in which a redundant memory cell and a redundant data line connected thereto are prepared, and a defective data line is replaced with the redundant data line. As a data line replacing method of this type, a data line shift method is generally used. In the data line shift method, a defective data line is replaced with an adjacent data line, and the replaced data line is replaced with another adjacent data line, the replacing process is repeated, and the last data line is replaced with a redundant data line.
FIG. 11 shows an example of a semiconductor memory device using a conventional data line shift method. This semiconductor memory device has a memory cell array 110 and a redundant memory cell array 120. Address signals are supplied to the memory cell array 110 and the redundant memory cell array 120 as a column address signal 130 and a row address signal 140, respectively. Data lines 150, 151, 152, 153, 154, . . . , 1515 having 16-bit data width are connected to the memory cell array 110, and a redundant data line 160 is connected to the redundant memory cell array 120. Data read from the memory cell array 110 depending on the address signals 130 and 140 are supplied to a switch circuit group 170 through the data lines 150, . . . , 1515. The switch circuit group 170 has switches SW0 . . . SW15. The input terminal of the switch SW0 is connected to the redundant data line 160 and the data line 150, and the input terminals of the switches SW1, . . . SW15 are connected to two adjacent data lines. The output terminals of the switches SW0, . . . SW15 are connected to data input/output line IO0, IO1, . . . , IO15, respectively. Decode circuits D0, . . . , D15 constituting a decoder group 180 are connected to the switches SW0, . . . SW15, and connection points between fuses 191 and resistors 192 constituting a fuse circuit group 190 are connected to the decode circuits D0, . . . , D15, respectively.
In the arrangement described above, when the memory cell array 110 has a defective memory cell, a fuse corresponding to the data line to which the defective memory cell is connected is cut. For example, if the data line 154 has a defect, in correspondence with this, the fuse connected to the decode circuit D4 is cut. At this time, depending on an output signal from the decode circuit D4 corresponding to the fuse, the switch SW4 connects the adjacent data line 153 to the data input/output line IO4 to relief the defective data line 154 by the non-defective data line 153. In accordance with this, signals are sequentially transmitted from the decode circuit D4 to the decoder D0, and the switches SW3, . . . , SW0 are switched by the decoders D4, . . . , D0. For this reason, the switch SW3 connects the data line 152 to the data input/output line IO3, and the switch SW2 connects the data line 151 to the data input/output line IO2. In this manner, the respective switches are switched, so that each switch selects an adjacent data line. The last switch SW0 connects the redundant data line 160 to the data input/output line IO0. As described above, the defective data line 154 is relieved.
In relief of a defective memory cell by the data line shift method shown in FIG. 11, since only one data line is relieved depending on an input address, relieving efficiency does not sufficiently increase. More specifically, data lines except for the data line corresponding to a decode circuit connected to the cut fuse cannot be relieved. For this reason, in order to improve the relieving efficient, a method in which different defective data lines can be replaced depending on input addresses.
FIG. 12 shows another example of a conventional semiconductor memory device, and shows an example in which a redundant data line can be replaced with a plurality of defective data lines. FIG. 12 shows a circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 7-114800. The same reference numerals as in FIG. 11 denote the same parts in FIG. 12. In case of this example, one terminals of switches 210a constituting a first switch circuit group 210 are connected to a redundant data line 160. One terminals of switches 220a constituting a second switch group 220 are connected to data lines 150, 151, 152, 153, 154, . . . , 1515, respectively. The other terminals of the switches 210a of the first switch circuit group 210 and the other terminals of the switches 220a of the second switch group 220 are connected to corresponding data input/output line IO0, . . . , IO15. The switches 210a of the first switch circuit group 210 are controlled by output signals from decode circuits D0, . . . , D15 constituting a decoder group 230, and the switches 220a of the second switch group 220 are controlled by inverted output signals from the decode circuits D0, . . . , D15 constituting the decoder group 230. The decode circuits D0, . . . , D15 are connected to a defective address memory circuit (F) 240. The defective address memory circuit 240 holds defective addresses, and outputs a signal of a plurality of bits when an input address coincides with an address held in the defective address memory circuit 240. The decode circuits D0, . . . , D15 generally turn on the switches of the second switch group 220 depending on output signals from the defective address memory circuit 240 and set the switches of the first switch circuit group 210 in an OFF state. On the other hand, when a defective address held in the defective address memory circuit 240 coincides with an input address, an output signal from the corresponding decode circuit is inverted depending on an output signal from the defective address memory circuit 240. For example, when the data line 151 has a defect, and an output signal from the decode circuit D1 is inverted, the data line 151 is disconnected from the data input/output line I01 to be connected to the redundant data line 160. Therefore, the data line 151 is relieved by the redundant data line 160.
In case of this example, a defective data line can be relieved depending on an input address. In addition, when a defective address is supplied, a data line connected to the defective memory cell is instantaneously switched to a redundant data line. For this reason, data transfer has a time margin. However, when a data width becomes large, the length of the redundant data line 160 increases. Therefore, a wiring capacity increases, and it is expected that high-speed data transfer cannot be easily performed.